Abstract
An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.
Original language | English |
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Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
Pages | 171-172 |
Number of pages | 2 |
DOIs | |
Publication status | Published - 2010 |
Externally published | Yes |
Event | 2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI Duration: 2010 Jun 16 → 2010 Jun 18 |
Other
Other | 2010 24th Symposium on VLSI Circuits, VLSIC 2010 |
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City | Honolulu, HI |
Period | 10/6/16 → 10/6/18 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials