A 600-MHz 54 × 54-bit multiplier with rectangular-styled Wallace tree

N. Itoh*, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, Y. Horiba

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

50 Citations (Scopus)


This paper presents an efficient layout method for a high-speed multiplier. The Wallace-tree method is generally used for high-speed multipliers. In the conventional Wallace tree, however, every partial product is added in a single direction from top to bottom. Therefore, the number of adders increases as the adding stage moves forward. As a result, it generates a dead area when the multiplier is laid out in a rectangle. To solve this problem, we propose a rectangular Wallace-tree construction method. In our method, the partial products are divided into two groups and added in the opposite direction. The partial products in the first group are added downward, and the partial products in the second group are added upward. Using this method, we eliminate the dead area. Also, we optimized the carry propagation between the two groups to realize high speed and a simple layout. We applied it to a 54 × 54-bit multiplier. The 980 μm × 1000 μm area size and the 600-MHz clock speed have been achieved using 0.18-μm CMOS technology.

Original languageEnglish
Pages (from-to)249-257
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number2
Publication statusPublished - 2001 Feb
Externally publishedYes


  • CMOS digital integrated circuits
  • Multiplication
  • Multiplying circuits
  • Redundant binary
  • Wallace tree

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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