A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; Masakazu Okada; Atsushi Ishii; Tsutomu Yoshihara; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/JSSC.2007.908004

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m² using 65 nm technology.

Original language	English
Pages (from-to)	96-108
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	43
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2007.908004
Publication status	Published - 2008 Jan
Externally published	Yes

Keywords

65 nm CMOS
6T-SRAM
CMOS
SRAM
embedded SRAM
fuse
known good die (KGD)
redundancy
wafer level burn-in

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2007.908004

Cite this

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Okada, M., Ishii, A., Yoshihara, T., Makino, H., Ishibashi, K., & Shinohara, H. (2008). A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE Journal of Solid-State Circuits, 43(1), 96-108. https://doi.org/10.1109/JSSC.2007.908004

Ohbayashi, S, Yabuuchi, M, Kono, K, Oda, Y, Imaoka, S, Usui, K, Yonezu, T, Iwamoto, T, Nii, K, Tsukamoto, Y, Arakawa, M, Uchida, T, Okada, M, Ishii, A, Yoshihara, T, Makino, H, Ishibashi, K & Shinohara, H 2008, 'A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die', IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 96-108. https://doi.org/10.1109/JSSC.2007.908004

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title = "A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die",

abstract = "We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.",

keywords = "65 nm CMOS, 6T-SRAM, CMOS, SRAM, embedded SRAM, fuse, known good die (KGD), redundancy, wafer level burn-in",

author = "Shigeki Ohbayashi and Makoto Yabuuchi and Kazushi Kono and Yuji Oda and Susumu Imaoka and Keiichi Usui and Toshiaki Yonezu and Takeshi Iwamoto and Koji Nii and Yasumasa Tsukamoto and Masashi Arakawa and Takahiro Uchida and Masakazu Okada and Atsushi Ishii and Tsutomu Yoshihara and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",

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AU - Ohbayashi, Shigeki

AU - Yabuuchi, Makoto

AU - Kono, Kazushi

AU - Oda, Yuji

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Yonezu, Toshiaki

AU - Iwamoto, Takeshi

AU - Nii, Koji

AU - Tsukamoto, Yasumasa

AU - Arakawa, Masashi

AU - Uchida, Takahiro

AU - Okada, Masakazu

AU - Ishii, Atsushi

AU - Yoshihara, Tsutomu

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

PY - 2008/1

Y1 - 2008/1

N2 - We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.

AB - We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.

KW - 65 nm CMOS

KW - 6T-SRAM

KW - CMOS

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KW - embedded SRAM

KW - fuse

KW - known good die (KGD)

KW - redundancy

KW - wafer level burn-in

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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Abstract

Keywords

ASJC Scopus subject areas

UN SDGs

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