A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; Masakazu Qkada; Atsushi Ishii; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/ISSCC.2007.373507

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi^*, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	488-490
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373507
Publication status	Published - 2007
Externally published	Yes
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373507

Cite this

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Qkada, M., Ishii, A., Makino, H., Ishibashi, K., & Shinohara, H. (2007). A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 488-490). Article 4242478 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373507

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. / Ohbayashi, Shigeki; Yabuuchi, Makoto; Kono, Kazushi et al.
2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 488-490 4242478 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohbayashi, S, Yabuuchi, M, Kono, K, Oda, Y, Imaoka, S, Usui, K, Yonezu, T, Iwamoto, T, Nii, K, Tsukamoto, Y, Arakawa, M, Uchida, T, Qkada, M, Ishii, A, Makino, H, Ishibashi, K & Shinohara, H 2007, A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242478, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 488-490, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373507

Ohbayashi S, Yabuuchi M, Kono K, Oda Y, Imaoka S, Usui K et al. A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 488-490. 4242478. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373507

Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Kono, Kazushi et al. / A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 488-490 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.",

author = "Shigeki Ohbayashi and Makoto Yabuuchi and Kazushi Kono and Yuji Oda and Susumu Imaoka and Keiichi Usui and Toshiaki Yonezu and Takeshi Iwamoto and Koji Nii and Yasumasa Tsukamoto and Masashi Arakawa and Takahiro Uchida and Masakazu Qkada and Atsushi Ishii and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",

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AU - Oda, Yuji

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Yonezu, Toshiaki

AU - Iwamoto, Takeshi

AU - Nii, Koji

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AU - Uchida, Takahiro

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AB - A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

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A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

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