TY - JOUR
T1 - A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor
AU - Zhang, Shuping
AU - Zhou, Jinjia
AU - Zhou, Dajiang
AU - Kimura, Shinji
AU - Goto, Satoshi
N1 - Funding Information:
This research is supported by the regional innovation strategy support program of MEXT, the Waseda University Graduate Program for Embodiment Informatics (FY2013-FY2019), and VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc & Cadence Design Systems, Inc. The work is also supported in part by a fund from NEC.
Publisher Copyright:
© 2017 The Institute of Electronics, Information and Communication Engineers.
PY - 2017/3
Y1 - 2017/3
N2 - In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D largescale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.
AB - In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D largescale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.
KW - 3D IC design
KW - Hamburger architecture
KW - Memory stacking
KW - Motion estimation processor
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U2 - 10.1587/transele.E100.C.223
DO - 10.1587/transele.E100.C.223
M3 - Article
AN - SCOPUS:85016075653
SN - 0916-8524
VL - E100C
SP - 223
EP - 231
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
IS - 3
ER -