A 98 GMACs/W 32-core vector processor in 65 nm CMOS

Xun He; Xin Jin; Minghui Wang; Dajiang Zhou; Satoshi Goto

doi:10.1587/transfun.E94.A.2609

A 98 GMACs/W 32-core vector processor in 65 nm CMOS

Xun He^*, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BWin average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm ² in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

Original language	English
Pages (from-to)	2609-2618
Number of pages	10
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E94-A
Issue number	12
DOIs	https://doi.org/10.1587/transfun.E94.A.2609
Publication status	Published - 2011 Dec

Keywords

Cache coherence
GMACs
Multicore processor
NoC
SIMD

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Graphics and Computer-Aided Design
Applied Mathematics
Signal Processing

Access to Document

10.1587/transfun.E94.A.2609

Cite this

@article{338b4871c299400980525d6e6ac1827e,

title = "A 98 GMACs/W 32-core vector processor in 65 nm CMOS",

abstract = "This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BWin average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm 2 in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.",

keywords = "Cache coherence, GMACs, Multicore processor, NoC, SIMD",

author = "Xun He and Xin Jin and Minghui Wang and Dajiang Zhou and Satoshi Goto",

year = "2011",

month = dec,

doi = "10.1587/transfun.E94.A.2609",

language = "English",

volume = "E94-A",

pages = "2609--2618",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "12",

}

TY - JOUR

T1 - A 98 GMACs/W 32-core vector processor in 65 nm CMOS

AU - He, Xun

AU - Jin, Xin

AU - Wang, Minghui

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2011/12

Y1 - 2011/12

N2 - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BWin average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm 2 in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

AB - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BWin average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm 2 in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

KW - Cache coherence

KW - GMACs

KW - Multicore processor

KW - NoC

KW - SIMD

UR - http://www.scopus.com/inward/record.url?scp=82655175636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=82655175636&partnerID=8YFLogxK

U2 - 10.1587/transfun.E94.A.2609

DO - 10.1587/transfun.E94.A.2609

M3 - Article

AN - SCOPUS:82655175636

SN - 0916-8508

VL - E94-A

SP - 2609

EP - 2618

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IS - 12

ER -

A 98 GMACs/W 32-core vector processor in 65 nm CMOS

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this