A 995Mpixels/s 0.2nJ/pixel fractional motion estimation architecture in HEVC for Ultra-HD

Gang He; Dajiang Zhou; Zhixiang Chen; Tianruo Zhang; Satoshi Goto

doi:10.1109/ASSCC.2013.6691042

A 995Mpixels/s 0.2nJ/pixel fractional motion estimation architecture in HEVC for Ultra-HD

Gang He, Dajiang Zhou, Zhixiang Chen, Tianruo Zhang, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

This paper presents a fractional motion estimation (FME) design in high efficiency video coding (HEVC) for ultrahigh definition video (Ultra-HD). To reduce complexity and achieve high throughput, the design is co-optimized in algorithm and hardware architecture. Bilinear quarter pixel approximation, together with a 5T12S search pattern is proposed to reduce the complexity of the interpolation and search process. Furthermore, we introduce an exhaustive size-hadamard transform (ES-HAD), to improve coding quality, and determine the best transform size rather than using complex transform coding. Besides, a data reuse method of ES-HAD is applied to reduce the hardware overhead. This design is implemented in 65nm CMOS chip and verified by FPGA based evaluation system. It achieves 995Mpixels/s for 7680×4320 30fps encoding, at least 4.7 times faster than previous designs. Its power dissipation is 198.6mW at 188MHz, with 0.2nJ/pixel power efficiency. Despite high complexity in HEVC, the chip achieves 56% improvement on power efficiency than previous works in H.264.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages	301-304
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2013.6691042
Publication status	Published - 2013
Event	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore Duration: 2013 Nov 11 → 2013 Nov 13

Other

Other	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
City	Singapore
Period	13/11/11 → 13/11/13

Keywords

FME
Hardware architecture
HEVC
Ultra-HD

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/ASSCC.2013.6691042

Cite this

He, G, Zhou, D, Chen, Z, Zhang, T & Goto, S 2013, A 995Mpixels/s 0.2nJ/pixel fractional motion estimation architecture in HEVC for Ultra-HD. in Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013., 6691042, pp. 301-304, 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, 13/11/11. https://doi.org/10.1109/ASSCC.2013.6691042

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abstract = "This paper presents a fractional motion estimation (FME) design in high efficiency video coding (HEVC) for ultrahigh definition video (Ultra-HD). To reduce complexity and achieve high throughput, the design is co-optimized in algorithm and hardware architecture. Bilinear quarter pixel approximation, together with a 5T12S search pattern is proposed to reduce the complexity of the interpolation and search process. Furthermore, we introduce an exhaustive size-hadamard transform (ES-HAD), to improve coding quality, and determine the best transform size rather than using complex transform coding. Besides, a data reuse method of ES-HAD is applied to reduce the hardware overhead. This design is implemented in 65nm CMOS chip and verified by FPGA based evaluation system. It achieves 995Mpixels/s for 7680×4320 30fps encoding, at least 4.7 times faster than previous designs. Its power dissipation is 198.6mW at 188MHz, with 0.2nJ/pixel power efficiency. Despite high complexity in HEVC, the chip achieves 56% improvement on power efficiency than previous works in H.264.",

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AU - Goto, Satoshi

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AB - This paper presents a fractional motion estimation (FME) design in high efficiency video coding (HEVC) for ultrahigh definition video (Ultra-HD). To reduce complexity and achieve high throughput, the design is co-optimized in algorithm and hardware architecture. Bilinear quarter pixel approximation, together with a 5T12S search pattern is proposed to reduce the complexity of the interpolation and search process. Furthermore, we introduce an exhaustive size-hadamard transform (ES-HAD), to improve coding quality, and determine the best transform size rather than using complex transform coding. Besides, a data reuse method of ES-HAD is applied to reduce the hardware overhead. This design is implemented in 65nm CMOS chip and verified by FPGA based evaluation system. It achieves 995Mpixels/s for 7680×4320 30fps encoding, at least 4.7 times faster than previous designs. Its power dissipation is 198.6mW at 188MHz, with 0.2nJ/pixel power efficiency. Despite high complexity in HEVC, the chip achieves 56% improvement on power efficiency than previous works in H.264.

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KW - Hardware architecture

KW - HEVC

KW - Ultra-HD

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A 995Mpixels/s 0.2nJ/pixel fractional motion estimation architecture in HEVC for Ultra-HD

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