A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding

Jinjia Zhou; Dajiang Zhou; Gang He; Satoshi Goto

doi:10.1007/978-3-642-15696-0_6

A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding

Jinjia Zhou^*, Dajiang Zhou, Gang He, Satoshi Goto

^*Corresponding author for this work

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding component is proposed to save the DRAM traffic. In this component, the motion information including motion vector and reference index, for the co-located picture and the last decoded line, is stored in DRAM. In order to save the DRAM access, a partition based storage format is first applied to condense the MB level data. Then, a DPCM-based variable length coding method is utilized to reduce the data size of each partition. Finally, the total bandwidth is further reduced by combining the co-located and last-line information. Experimental results show that the bandwidth requirement for motion vector calculation can be reduced by 85%~98% on typical 1080p and QFHD sequences, with only 7.8k additional logic gates. This can contribute to near 20% bandwidth reduction for the whole video decoder system.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Pages	52-61
Number of pages	10
Volume	6298 LNCS
Edition	PART 2
DOIs	https://doi.org/10.1007/978-3-642-15696-0_6
Publication status	Published - 2010
Event	11th Pacific Rim Conference on Multimedia, PCM 2010 - Shanghai Duration: 2010 Sept 21 → 2010 Sept 24

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Number	PART 2
Volume	6298 LNCS
ISSN (Print)	03029743
ISSN (Electronic)	16113349

Other

Other	11th Pacific Rim Conference on Multimedia, PCM 2010
City	Shanghai
Period	10/9/21 → 10/9/24

Keywords

DRAM bandwidth
H.264/AVC
Motion vector decoding
ultra high resolution
variable length coding

ASJC Scopus subject areas

Computer Science(all)
Theoretical Computer Science

Access to Document

10.1007/978-3-642-15696-0_6

Cite this

Zhou, J., Zhou, D., He, G., & Goto, S. (2010). A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (PART 2 ed., Vol. 6298 LNCS, pp. 52-61). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6298 LNCS, No. PART 2). https://doi.org/10.1007/978-3-642-15696-0_6

A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding. / Zhou, Jinjia; Zhou, Dajiang; He, Gang et al.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 6298 LNCS PART 2. ed. 2010. p. 52-61 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6298 LNCS, No. PART 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhou, J, Zhou, D, He, G & Goto, S 2010, A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 2 edn, vol. 6298 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), no. PART 2, vol. 6298 LNCS, pp. 52-61, 11th Pacific Rim Conference on Multimedia, PCM 2010, Shanghai, 10/9/21. https://doi.org/10.1007/978-3-642-15696-0_6

Zhou J, Zhou D, He G, Goto S. A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 2 ed. Vol. 6298 LNCS. 2010. p. 52-61. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 2). doi: 10.1007/978-3-642-15696-0_6

Zhou, Jinjia ; Zhou, Dajiang ; He, Gang et al. / A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 6298 LNCS PART 2. ed. 2010. pp. 52-61 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 2).

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A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding

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