TY - GEN
T1 - A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing
AU - Ye, Jinghao
AU - Yanagisawa, Masao
AU - Shi, Youhua
PY - 2019/11
Y1 - 2019/11
N2 - A high-speed FIR filter structure is proposed in this paper by utilizing bit-segmentation adders and symmetric transpose 2-block FIR structure. First, a bit-segmented adder chain-based design is proposed with bit-segmentation adders. Second, a basic unit design of symmetric transpose block FIR is proposed to reduce the critical path delay. The evaluation results show that, when compared with state-of-the-art high-speed CSD multiplier-based FIR filter design, the proposed design requires 14.1% less area while provides 7.9% frequency improvement, 10.2% reduction of power consumption, 22.8% reduction of energy-delay-product and 20.4% reduction of area-delay-product, which shows the effectiveness of the proposed method.
AB - A high-speed FIR filter structure is proposed in this paper by utilizing bit-segmentation adders and symmetric transpose 2-block FIR structure. First, a bit-segmented adder chain-based design is proposed with bit-segmentation adders. Second, a basic unit design of symmetric transpose block FIR is proposed to reduce the critical path delay. The evaluation results show that, when compared with state-of-the-art high-speed CSD multiplier-based FIR filter design, the proposed design requires 14.1% less area while provides 7.9% frequency improvement, 10.2% reduction of power consumption, 22.8% reduction of energy-delay-product and 20.4% reduction of area-delay-product, which shows the effectiveness of the proposed method.
KW - bit-segmentation adder
KW - FIR filter
KW - high speed
UR - http://www.scopus.com/inward/record.url?scp=85078707597&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85078707597&partnerID=8YFLogxK
U2 - 10.1109/APCCAS47518.2019.8953124
DO - 10.1109/APCCAS47518.2019.8953124
M3 - Conference contribution
AN - SCOPUS:85078707597
T3 - Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
SP - 29
EP - 32
BT - Proceedings - APCCAS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
Y2 - 11 November 2019 through 14 November 2019
ER -
