A built‐in self‐test structure for arithmetic execution units of VLSIs

Takeshi Ikenaga*, Jun‐Ichi ‐I Takahashi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This paper proposes advanced built‐in self‐test (BIST) structures: a bit‐distributed pattern generator (BDPG) and a multistage space compressor (MSSC) for arithmetic execution units of VLSIs. By focusing on the regularity of the arithmetic execution units, the required area overhead of the BIST circuits is less than that of conventional ones. The experimental result shows that these structures can reduce almost 60 percent of the hardware overhead of conventional BIST circuits while maintaining high‐fault coverage. These BIST configurations will make a significant contribution to test cost reduction for the performance‐orientation digital LSIs, especially digital signal processor LSIs.

Original languageEnglish
Pages (from-to)68-78
Number of pages11
JournalElectronics and Communications in Japan (Part II: Electronics)
Issue number4
Publication statusPublished - 1995 Apr
Externally publishedYes


  • Design for testability
  • arithmetic execution unit
  • built‐in self‐test
  • error‐masking rate
  • fault coverage

ASJC Scopus subject areas

  • General Physics and Astronomy
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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