A CABAC encoding core with dynamic pipeline for H.264/AVC main profile

Lingfeng Li; Yang Song; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/APCCAS.2006.342119

A CABAC encoding core with dynamic pipeline for H.264/AVC main profile

Lingfeng Li^*, Yang Song, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

25 Citations (Scopus)

Abstract

This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	760-763
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342119
Publication status	Published - 2006 Dec 1
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 2006 Dec 4 → 2006 Dec 6

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	06/12/4 → 06/12/6

Keywords

Architecture
CABAC
H.264
Pipeline

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2006.342119

Cite this

A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. / Li, Lingfeng; Song, Yang; Ikenaga, Takeshi et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 760-763 4145504 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, L, Song, Y, Ikenaga, T & Goto, S 2006, A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145504, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 760-763, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342119

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abstract = "This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.",

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N2 - This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

AB - This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

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KW - Pipeline

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A CABAC encoding core with dynamic pipeline for H.264/AVC main profile

Abstract

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Keywords

ASJC Scopus subject areas

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