A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

Mathematics

• Field Programmable Gate Array 100%
• Critical Path 75%
• Partitioning 63%
• Chip 50%
• Path 43%
• Assign 15%
• Logic 12%
• Output 11%
• Network Flow 10%
• Experimental Results 7%
• Resolve 7%
• Benchmark 7%
• Decrease 6%
• Upper and Lower Bounds 6%
• Lower bound 5%
• Upper bound 5%
• Demonstrate 4%

Engineering & Materials Science

• Field programmable gate arrays (FPGA) 51%
• Networks (circuits) 34%