A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Hiroshi Fuketa*, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)


In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

Original languageEnglish
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9781450306362
Publication statusPublished - 2011
Externally publishedYes

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


  • Minimum operating voltage
  • subthreshold circuits
  • variations

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation


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