A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Jing Wang; Hirofumi Shinohara

doi:10.1109/VLSI-DAT.2019.8741737

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Jing Wang, Hirofumi Shinohara

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage V_ref and output current I_ref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the V_ref and I_ref are 0.74%/V and 4.15%/V, respectively.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741737
Publication status	Published - 2019 Apr
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan, Province of China Duration: 2019 Apr 22 → 2019 Apr 25

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	19/4/22 → 19/4/25

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/VLSI-DAT.2019.8741737

Cite this

Wang, J., & Shinohara, H. (2019). A CMOS 0.85-V 15.8-nW current and voltage reference without resistors. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 Article 8741737 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741737

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors. / Wang, Jing; Shinohara, Hirofumi.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741737 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, J & Shinohara, H 2019, A CMOS 0.85-V 15.8-nW current and voltage reference without resistors. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741737, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, Province of China, 19/4/22. https://doi.org/10.1109/VLSI-DAT.2019.8741737

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abstract = "In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage Vref and output current Iref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the Vref and Iref are 0.74%/V and 4.15%/V, respectively.",

author = "Jing Wang and Hirofumi Shinohara",

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N2 - In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage Vref and output current Iref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the Vref and Iref are 0.74%/V and 4.15%/V, respectively.

AB - In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage Vref and output current Iref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the Vref and Iref are 0.74%/V and 4.15%/V, respectively.

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BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

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T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

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ER -

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Abstract

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