A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

Zhangcai Huang; Qin Luo; Yasuaki Inoue

doi:10.1109/ISCAS.2010.5537636

A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

Zhangcai Huang^*, Qin Luo, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

28 Citations (Scopus)

Abstract

In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages	4069-4072
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537636
Publication status	Published - 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris Duration: 2010 May 30 → 2010 Jun 2

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
City	Paris
Period	10/5/30 → 10/6/2

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2010.5537636

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Huang, Z, Luo, Q & Inoue, Y 2010, A CMOS sub-1-V nanopower current and voltage reference with leakage compensation. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537636, pp. 4069-4072, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537636

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AU - Huang, Zhangcai

AU - Luo, Qin

AU - Inoue, Yasuaki

PY - 2010

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N2 - In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW.

AB - In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW.

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A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

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