A CMOS voltage reference combining body effect with switched-current technique

Ning Ren; Hao Zhang; Tsutomu Yoshihara

doi:10.1109/ISOCC.2012.6407047

A CMOS voltage reference combining body effect with switched-current technique

Ning Ren^*, Hao Zhang, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V _BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	92-95
Number of pages	4
DOIs	https://doi.org/10.1109/ISOCC.2012.6407047
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island Duration: 2012 Nov 4 → 2012 Nov 7

Other

Other	2012 International SoC Design Conference, ISOCC 2012
City	Jeju Island
Period	12/11/4 → 12/11/7

Keywords

body effect
CMOS voltage reference
subthreshold
switched-current technique

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC.2012.6407047

Cite this

@inproceedings{c997db200dfe4fc6aca42880cfa307d9,

title = "A CMOS voltage reference combining body effect with switched-current technique",

abstract = "A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.",

keywords = "body effect, CMOS voltage reference, subthreshold, switched-current technique",

author = "Ning Ren and Hao Zhang and Tsutomu Yoshihara",

year = "2012",

doi = "10.1109/ISOCC.2012.6407047",

language = "English",

isbn = "9781467329880",

pages = "92--95",

booktitle = "ISOCC 2012 - 2012 International SoC Design Conference",

note = "2012 International SoC Design Conference, ISOCC 2012 ; Conference date: 04-11-2012 Through 07-11-2012",

}

TY - GEN

T1 - A CMOS voltage reference combining body effect with switched-current technique

AU - Ren, Ning

AU - Zhang, Hao

AU - Yoshihara, Tsutomu

PY - 2012

Y1 - 2012

N2 - A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.

AB - A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.

KW - body effect

KW - CMOS voltage reference

KW - subthreshold

KW - switched-current technique

UR - http://www.scopus.com/inward/record.url?scp=84873980203&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84873980203&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2012.6407047

DO - 10.1109/ISOCC.2012.6407047

M3 - Conference contribution

AN - SCOPUS:84873980203

SN - 9781467329880

SP - 92

EP - 95

BT - ISOCC 2012 - 2012 International SoC Design Conference

T2 - 2012 International SoC Design Conference, ISOCC 2012

Y2 - 4 November 2012 through 7 November 2012

ER -

A CMOS voltage reference combining body effect with switched-current technique

Abstract

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Keywords

ASJC Scopus subject areas

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