A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara

doi:10.1109/JSSC.2004.838016

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

Hideyuki Noda^*, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

92 Citations (Scopus)

Abstract

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm ². In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm² for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

Original language	English
Pages (from-to)	245-251
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	40
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2004.838016
Publication status	Published - 2005 Jan

Keywords

CMOS memory integrated circuits
Embedded DRAM
Network
Ternary CAM

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2004.838016

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Noda, H., Inoue, K., Kuroiwa, M., Igaue, F., Yamamoto, K., Mattausch, H. J., Koide, T., Amo, A., Hachisuka, A., Soeda, S., Hayashi, I., Morishita, F., Dosaka, K., Arimoto, K., Fujishima, K., Anami, K., & Yoshihara, T. (2005). A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE Journal of Solid-State Circuits, 40(1), 245-251. https://doi.org/10.1109/JSSC.2004.838016

Noda, H, Inoue, K, Kuroiwa, M, Igaue, F, Yamamoto, K, Mattausch, HJ, Koide, T, Amo, A, Hachisuka, A, Soeda, S, Hayashi, I, Morishita, F, Dosaka, K, Arimoto, K, Fujishima, K, Anami, K & Yoshihara, T 2005, 'A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture', IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 245-251. https://doi.org/10.1109/JSSC.2004.838016

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abstract = "This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm 2. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm2 for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.",

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AU - Yamamoto, Kouji

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AU - Morishita, Fukashi

AU - Dosaka, Katsumi

AU - Arimoto, Kazutami

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AU - Anami, Kenji

AU - Yoshihara, Tsutomu

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N2 - This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm 2. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm2 for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

AB - This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm 2. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm2 for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

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A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

Abstract

Keywords

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