A fast lock phase-locked loop using a continuous-time phase frequency detector

Jun Pan; Tsutomu Yoshihara

doi:10.1109/EDSSC.2007.4450145

A fast lock phase-locked loop using a continuous-time phase frequency detector

Jun Pan^*, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	393-396
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450145
Publication status	Published - 2007
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan Duration: 2007 Dec 20 → 2007 Dec 22

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
City	Tainan
Period	07/12/20 → 07/12/22

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/EDSSC.2007.4450145

Cite this

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title = "A fast lock phase-locked loop using a continuous-time phase frequency detector",

abstract = "A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.",

author = "Jun Pan and Tsutomu Yoshihara",

year = "2007",

doi = "10.1109/EDSSC.2007.4450145",

language = "English",

isbn = "1424406374",

pages = "393--396",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

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T1 - A fast lock phase-locked loop using a continuous-time phase frequency detector

AU - Pan, Jun

AU - Yoshihara, Tsutomu

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N2 - A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

AB - A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

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SN - 1424406374

SN - 9781424406371

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BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

A fast lock phase-locked loop using a continuous-time phase frequency detector

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