TY - GEN
T1 - A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit
AU - Tsukamoto, Youhei
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
AU - Togawa, Nozomu
PY - 2010/12/1
Y1 - 2010/12/1
N2 - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.
AB - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.
UR - http://www.scopus.com/inward/record.url?scp=79959259404&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2010.5774956
DO - 10.1109/APCCAS.2010.5774956
M3 - Conference contribution
AN - SCOPUS:79959259404
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1083
EP - 1086
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -