A fault-secure high-level synthesis algorithm for RDR architectures

Sho Tanaka*, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


As device feature size decreases, the reliability improvement against soft errors becomes quite necessary. A fault-secure system, in which concurrent error detection is realized, is one of the solutions to this problem. On the other hand, average interconnection delays exceed gate delays which leads to a serious timing closure problem. By using regular-distributed-register architecture (RDR architecture), we can estimate interconnection delays very accurately and their influence can be much reduced even in behavioral-level design. In this paper, we propose a fault-secure high-level synthesis algorithm for an RDR architecture. In fault-secure high-level synthesis, a recomputation CDFG as well as a normal-computation CDFG must be scheduled to control steps and bound to functional units. Firstly, our algorithm re-uses vacant areas on RDR islands to allocate new function units additionally for the recomputation CDFG. Secondly, we propose an efficient edge-break algorithm which considers comparison nodes' scheduling/binding. We can have small-latency scheduling/binding for both the normal CDFG and recomputation CDFG. Our algorithm reduces the required control steps by up to 53% compared with the conventional approach.

Original languageEnglish
Pages (from-to)150-165
Number of pages16
JournalIPSJ Transactions on System LSI Design Methodology
Publication statusPublished - 2011

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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