Abstract
In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.
| Original language | English |
|---|---|
| Pages (from-to) | 735-740 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E84-A |
| Issue number | 3 |
| Publication status | Published - 2001 Mar |
| Externally published | Yes |
| Event | 13th Workshop on Circuits and Systems in Karuizawa - Karuizawa, Japan Duration: 2000 Apr 24 → 2000 Apr 25 |
Keywords
- Cooled logic
- Dual-rail logic
- Low-power
- Overlapped clock
- Pass transistor
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics