TY - GEN
T1 - A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM
AU - Minami, Yoshihiro
AU - Shino, Tomoaki
AU - Sakamoto, Atsushi
AU - Higashi, Tomoki
AU - Kusunoki, Naoki
AU - Fujita, Katsuyuki
AU - Hatsuda, Kosuke
AU - Ohsawa, Takashi
AU - Aoki, Nobutoshi
AU - Tanimoto, Hiroyoshi
AU - Morikado, Mutsuo
AU - Nakajima, Hiroomi
AU - Inoh, Kazumi
AU - Hamamoto, Takeshi
AU - Nitayama, Akihiro
PY - 2005/12/1
Y1 - 2005/12/1
N2 - A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.
AB - A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.
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M3 - Conference contribution
AN - SCOPUS:33847749901
SN - 078039268X
SN - 9780780392687
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 307
EP - 310
BT - IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
T2 - IEEE International Electron Devices Meeting, 2005 IEDM
Y2 - 5 December 2005 through 7 December 2005
ER -