A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Koichi Fujiwara, Kazushi Kawamura, Shin Ya Abe, Masao Yanagisawa, Nozomu Togawa

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

Original languageEnglish
Pages (from-to)1392-1405
Number of pages14
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number7
Publication statusPublished - 2015 Jul 1


  • FPGA
  • Floorplan
  • High-level synthesis (HLS)
  • Interconnection delay
  • MUX

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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