A fully integrated PLL frequency synthesizer LSI for mobile communication system

T. Yasunaga; S. Hirano; M. Maeda; Y. Hiraoka; T. Andou; Y. Miyahara

A fully integrated PLL frequency synthesizer LSI for mobile communication system

T. Yasunaga^*, S. Hirano, M. Maeda, Y. Hiraoka, T. Andou, Y. Miyahara

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170us.

Original language	English
Pages	65-68
Number of pages	4
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE Radio Frequency Integrated Circuits (RFIC) - Phoenix, AZ, United States Duration: 2001 May 20 → 2001 May 22

Conference

Conference	2001 IEEE Radio Frequency Integrated Circuits (RFIC)
Country/Territory	United States
City	Phoenix, AZ
Period	01/5/20 → 01/5/22

ASJC Scopus subject areas

Engineering(all)

Cite this

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abstract = "A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170us.",

author = "T. Yasunaga and S. Hirano and M. Maeda and Y. Hiraoka and T. Andou and Y. Miyahara",

year = "2001",

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note = "2001 IEEE Radio Frequency Integrated Circuits (RFIC) ; Conference date: 20-05-2001 Through 22-05-2001",

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T1 - A fully integrated PLL frequency synthesizer LSI for mobile communication system

AU - Yasunaga, T.

AU - Hirano, S.

AU - Maeda, M.

AU - Hiraoka, Y.

AU - Andou, T.

AU - Miyahara, Y.

PY - 2001

Y1 - 2001

N2 - A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170us.

AB - A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170us.

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M3 - Paper

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T2 - 2001 IEEE Radio Frequency Integrated Circuits (RFIC)

Y2 - 20 May 2001 through 22 May 2001

ER -

A fully integrated PLL frequency synthesizer LSI for mobile communication system

Abstract

Conference

ASJC Scopus subject areas

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