A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

Yihan Zhu, Takashi Ohsawa

Research output: Contribution to journalArticlepeer-review

Abstract

The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32 nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60 mV at 1 V power supply voltage for the −5σ cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160 mV and 440 mV for the −5σ cell, respectively, which are better than the 6TSRAM cell.

Original languageEnglish
Article numberSC1004
JournalJapanese journal of applied physics
Volume62
Issue numberSC
DOIs
Publication statusPublished - 2023 Apr 1

Keywords

  • effective oxide thickness (EOT)
  • gate leakage current
  • loadless 4T SRAM
  • static noise margin (SNM)

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy

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