A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC

Lingfeng Li*, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm 2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

Original languageEnglish
Pages (from-to)81-95
Number of pages15
JournalJournal of Signal Processing Systems
Issue number1
Publication statusPublished - 2008 Jan


  • Codec
  • H.264/AVC
  • VLSI architecture

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modelling and Simulation
  • Hardware and Architecture


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