Abstract
H.264 and AVS are the two latest video coding standards. Since the similarity between their structures, it is feasible to develop a dual-mode VLSI decoder for supporting both standards, with substantially less cost than the solution with two individual decoders. In this paper, we propose a dualstandard VLSI architecture for MC interpolation, which is the most calculation intensive module of the dual-mode decoder. By applying reconfigurable FIR filters and an adaptive pipeline strategy, an implementation of the architecture can process realtime video streams in 1280×720, 30fps at low cost (11.5k gates, no RAM). This design also provides scalability to meet higher performance requirements.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Pages | 2910-2913 |
| Number of pages | 4 |
| Publication status | Published - 2007 |
| Externally published | Yes |
| Event | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 2007 May 27 → 2007 May 30 |
Other
| Other | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 |
|---|---|
| Country/Territory | United States |
| City | New Orleans, LA |
| Period | 07/5/27 → 07/5/30 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering