A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Qian Xie; Qian He; Xiao Peng; Ying Cui; Zhixiang Chen; Dajiang Zhou; Satoshi Goto

doi:10.1109/SiPS.2011.6088961

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Qian Xie^*, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

Original language	English
Title of host publication	2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
Pages	122-127
Number of pages	6
DOIs	https://doi.org/10.1109/SiPS.2011.6088961
Publication status	Published - 2011
Event	2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut Duration: 2011 Oct 4 → 2011 Oct 7

Other

Other	2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
City	Beirut
Period	11/10/4 → 11/10/7

Keywords

high parallel
LDPC decoder
low power
matrix reordering

ASJC Scopus subject areas

Signal Processing

Access to Document

10.1109/SiPS.2011.6088961

Cite this

Xie, Q, He, Q, Peng, X, Cui, Y, Chen, Z, Zhou, D & Goto, S 2011, A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. in 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings., 6088961, pp. 122-127, 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Beirut, 11/10/4. https://doi.org/10.1109/SiPS.2011.6088961

@inproceedings{4ab39885bf9142f59e4e2dc44cdc7b19,

title = "A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering",

abstract = "This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.",

keywords = "high parallel, LDPC decoder, low power, matrix reordering",

author = "Qian Xie and Qian He and Xiao Peng and Ying Cui and Zhixiang Chen and Dajiang Zhou and Satoshi Goto",

year = "2011",

doi = "10.1109/SiPS.2011.6088961",

language = "English",

isbn = "9781457719219",

pages = "122--127",

booktitle = "2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings",

note = "2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 ; Conference date: 04-10-2011 Through 07-10-2011",

}

TY - GEN

T1 - A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

AU - Xie, Qian

AU - He, Qian

AU - Peng, Xiao

AU - Cui, Ying

AU - Chen, Zhixiang

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2011

Y1 - 2011

N2 - This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

AB - This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

KW - high parallel

KW - LDPC decoder

KW - low power

KW - matrix reordering

UR - http://www.scopus.com/inward/record.url?scp=84055177254&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84055177254&partnerID=8YFLogxK

U2 - 10.1109/SiPS.2011.6088961

DO - 10.1109/SiPS.2011.6088961

M3 - Conference contribution

AN - SCOPUS:84055177254

SN - 9781457719219

SP - 122

EP - 127

BT - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings

T2 - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011

Y2 - 4 October 2011 through 7 October 2011

ER -

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Abstract

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this