A high-performance CABAC encoder architecture for HEVC and H.264/AVC

Jinjia Zhou; Dajiang Zhou; Wei Fei; Satoshi Goto

doi:10.1109/ICIP.2013.6738323

A high-performance CABAC encoder architecture for HEVC and H.264/AVC

Jinjia Zhou, Dajiang Zhou, Wei Fei, Satoshi Goto

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.

Original language	English
Title of host publication	2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings
Pages	1568-1572
Number of pages	5
DOIs	https://doi.org/10.1109/ICIP.2013.6738323
Publication status	Published - 2013
Event	2013 20th IEEE International Conference on Image Processing, ICIP 2013 - Melbourne, VIC Duration: 2013 Sept 15 → 2013 Sept 18

Other

Other	2013 20th IEEE International Conference on Image Processing, ICIP 2013
City	Melbourne, VIC
Period	13/9/15 → 13/9/18

Keywords

CABAC
entropy coding
HEVC
UHDTV

ASJC Scopus subject areas

Computer Vision and Pattern Recognition

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10.1109/ICIP.2013.6738323

Cite this

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title = "A high-performance CABAC encoder architecture for HEVC and H.264/AVC",

abstract = "This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.",

keywords = "CABAC, entropy coding, HEVC, UHDTV",

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AU - Fei, Wei

AU - Goto, Satoshi

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N2 - This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.

AB - This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.

KW - CABAC

KW - entropy coding

KW - HEVC

KW - UHDTV

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A high-performance CABAC encoder architecture for HEVC and H.264/AVC

Abstract

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Keywords

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