TY - GEN
T1 - A high-performance circuit design algorithm using data dependent approximation
AU - Kawamura, Kazushi
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
N1 - Funding Information:
This research is supported in part by Grant-in-Aid for JSPS Fellows (No. 15J07118).
Publisher Copyright:
© 2016 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/12/27
Y1 - 2016/12/27
N2 - This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.
AB - This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.
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U2 - 10.1109/ISOCC.2016.7799750
DO - 10.1109/ISOCC.2016.7799750
M3 - Conference contribution
AN - SCOPUS:85010409235
T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
SP - 95
EP - 96
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th International SoC Design Conference, ISOCC 2016
Y2 - 23 October 2016 through 26 October 2016
ER -