A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama*, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)


A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

Original languageEnglish
Number of pages2
Publication statusPublished - 1990 Dec 1
Externally publishedYes
Event1990 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 1990 Jun 71990 Jun 9


Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA

ASJC Scopus subject areas

  • Engineering(all)


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