A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama; Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama

A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama^*, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

3 Citations (Scopus)

Abstract

A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

Original language	English
Pages	9-10
Number of pages	2
Publication status	Published - 1990 Dec 1
Externally published	Yes
Event	1990 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 1990 Jun 7 → 1990 Jun 9

Other

Other	1990 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	90/6/7 → 90/6/9

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "A high random-access-data-rate 4MbDRAM with pipeline operation",

abstract = "A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.",

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AU - Furuyama, Tohru

AU - Kushiyama, Natsuki

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Muraoka, Kazuyoshi

AU - Nagahama, Yousei

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

AB - A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

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T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

A high random-access-data-rate 4MbDRAM with pipeline operation

Abstract

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ASJC Scopus subject areas

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