A highly efficient inverse transform architecture for multi-standard HDTV decoder

Hang Zhang; Peilin Liu; Yu Hong; Dajiang Zhou; Satoshi Goto

doi:10.1109/ASICON.2009.5351634

A highly efficient inverse transform architecture for multi-standard HDTV decoder

Hang Zhang^*, Peilin Liu, Yu Hong, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.

Original language	English
Title of host publication	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages	525-528
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351634
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha Duration: 2009 Oct 20 → 2009 Oct 23

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
City	Changsha
Period	09/10/20 → 09/10/23

Keywords

Architecture
AVS and MPEG1/2/4
Distributed arithmetic
H.264/AVC
Inverse transform

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351634

Cite this

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title = "A highly efficient inverse transform architecture for multi-standard HDTV decoder",

abstract = "This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.",

keywords = "Architecture, AVS and MPEG1/2/4, Distributed arithmetic, H.264/AVC, Inverse transform",

author = "Hang Zhang and Peilin Liu and Yu Hong and Dajiang Zhou and Satoshi Goto",

year = "2009",

doi = "10.1109/ASICON.2009.5351634",

language = "English",

isbn = "9781424438686",

pages = "525--528",

booktitle = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

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T1 - A highly efficient inverse transform architecture for multi-standard HDTV decoder

AU - Zhang, Hang

AU - Liu, Peilin

AU - Hong, Yu

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.

AB - This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.

KW - Architecture

KW - AVS and MPEG1/2/4

KW - Distributed arithmetic

KW - H.264/AVC

KW - Inverse transform

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DO - 10.1109/ASICON.2009.5351634

M3 - Conference contribution

AN - SCOPUS:77949406713

SN - 9781424438686

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EP - 528

BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

A highly efficient inverse transform architecture for multi-standard HDTV decoder

Abstract

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Keywords

ASJC Scopus subject areas

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