A low-power soft error tolerant latch scheme

Saki Tajima; Youhua Shi; Nozomu Togawa; Masao Yanagisawa

doi:10.1109/ASICON.2015.7516885

A low-power soft error tolerant latch scheme

Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479984831
DOIs	https://doi.org/10.1109/ASICON.2015.7516885
Publication status	Published - 2016 Jul 19
Event	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Country/Territory	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2015.7516885

Cite this

Tajima, S, Shi, Y , Togawa, N & Yanagisawa, M 2016, A low-power soft error tolerant latch scheme. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516885, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516885

@inproceedings{7851166956e24d4f99329b325f1aaf1e,

title = "A low-power soft error tolerant latch scheme",

abstract = "As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.",

author = "Saki Tajima and Youhua Shi and Nozomu Togawa and Masao Yanagisawa",

year = "2016",

month = jul,

day = "19",

doi = "10.1109/ASICON.2015.7516885",

language = "English",

booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",

}

TY - GEN

T1 - A low-power soft error tolerant latch scheme

AU - Tajima, Saki

AU - Shi, Youhua

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

PY - 2016/7/19

Y1 - 2016/7/19

N2 - As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

AB - As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

UR - http://www.scopus.com/inward/record.url?scp=84982292448&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84982292448&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2015.7516885

DO - 10.1109/ASICON.2015.7516885

M3 - Conference contribution

AN - SCOPUS:84982292448

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015

Y2 - 3 November 2015 through 6 November 2015

ER -

A low-power soft error tolerant latch scheme

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this