A low-power VLSI architecture for HEVC de-quantization and inverse transform

Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


In this paper, we present a low-power system for the de- quantization and inverse transform of HEVC. Firstly, we present a low-delay circuit to process the coded results of the syntax elements, and then reduce the number of multipliers from 16 to 4 for the de-quantization process of each 4x4 block. Secondly, we give two efficient data mapping schemes for the memory between de-quantization and inverse transform, and the memory for transpose. Thirdly, the zero information is utilized through the whole system. For two memory parts, the write and read operation of zero blocks/ rows/ coefficients can all be skipped to save the power consumption. The results show that up to 86% power consumption can be saved for the memory part under the configuration of "Random-access" and common QPs. For the logical part, the proposed architecture for de-quantization can reduce 77% area consumption. Overall, our system can support real-time coding for 8K x 4K 120 fps video sequences and the normalized area consumption can be reduced by 68% compared with the latest work.

Original languageEnglish
Pages (from-to)2375-2387
Number of pages13
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
Publication statusPublished - 2016 Dec


  • De-quantization
  • HEVC
  • Inverse transform
  • Low-cost
  • Low-power
  • Video coding

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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