A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Zhixiang Chen; Xiao Peng; Xiongxin Zhao; Qian Xie; Leona Okamura; Dajiang Zhou; Satoshi Goto

doi:10.1109/VDAT.2011.5783634

A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Zhixiang Chen^*, Xiao Peng, Xiongxin Zhao, Qian Xie, Leona Okamura, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bit-iter.

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	298-301
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783634
Publication status	Published - 2011
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu Duration: 2011 Apr 25 → 2011 Apr 28

Other

Other	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
City	Hsinchu
Period	11/4/25 → 11/4/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VDAT.2011.5783634

Cite this

Chen, Z, Peng, X, Zhao, X, Xie, Q, Okamura, L, Zhou, D & Goto, S 2011, A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783634, pp. 298-301, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, 11/4/25. https://doi.org/10.1109/VDAT.2011.5783634

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AU - Chen, Zhixiang

AU - Peng, Xiao

AU - Zhao, Xiongxin

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AU - Okamura, Leona

AU - Zhou, Dajiang

AU - Goto, Satoshi

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AB - In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bit-iter.

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A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Abstract

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ASJC Scopus subject areas

UN SDGs

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