A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

Takashi Ohsawa*, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Kazumi Inoh, Takeshi Hamamoto

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

12 Citations (Scopus)


A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2 with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

Original languageEnglish
Number of pages4
Publication statusPublished - 2003
Externally publishedYes
Event2003 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2003 Jun 122003 Jun 14


Other2003 Symposium on VLSI Circuits

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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