A new 7-transistor SRAM cell design with high read stability

Yen Hsiang Tseng; Yimeng Zhang; Leona Okamura; Tsutomu Yoshihara

doi:10.1109/ICEDSA.2010.5503104

A new 7-transistor SRAM cell design with high read stability

Yen Hsiang Tseng, Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

Original language	English
Title of host publication	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
Pages	43-47
Number of pages	5
DOIs	https://doi.org/10.1109/ICEDSA.2010.5503104
Publication status	Published - 2010
Event	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur Duration: 2010 Apr 12 → 2010 Apr 13

Other

Other	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
City	Kuala Lumpur
Period	10/4/12 → 10/4/13

Keywords

Static Noise Margin (SNM)
Static Random Access Memory (SRAM)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICEDSA.2010.5503104

Cite this

Tseng, YH, Zhang, Y, Okamura, L & Yoshihara, T 2010, A new 7-transistor SRAM cell design with high read stability. in 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings., 5503104, pp. 43-47, 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010, Kuala Lumpur, 10/4/12. https://doi.org/10.1109/ICEDSA.2010.5503104

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title = "A new 7-transistor SRAM cell design with high read stability",

abstract = "The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.",

keywords = "Static Noise Margin (SNM), Static Random Access Memory (SRAM)",

author = "Tseng, {Yen Hsiang} and Yimeng Zhang and Leona Okamura and Tsutomu Yoshihara",

year = "2010",

doi = "10.1109/ICEDSA.2010.5503104",

language = "English",

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T1 - A new 7-transistor SRAM cell design with high read stability

AU - Tseng, Yen Hsiang

AU - Zhang, Yimeng

AU - Okamura, Leona

AU - Yoshihara, Tsutomu

PY - 2010

Y1 - 2010

N2 - The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

AB - The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

KW - Static Noise Margin (SNM)

KW - Static Random Access Memory (SRAM)

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BT - 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings

T2 - 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010

Y2 - 12 April 2010 through 13 April 2010

ER -

A new 7-transistor SRAM cell design with high read stability

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Keywords

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