A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM

Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Hideaki Arima; Tsutomu Yoshihara

doi:10.1109/4.261

A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

Research output: Contribution to journal › Article › peer-review

Abstract

A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.

Original language	English
Pages (from-to)	86-90
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	23
Issue number	1
DOIs	https://doi.org/10.1109/4.261
Publication status	Published - 1988
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.261

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title = "A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM",

abstract = "A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.",

author = "Yasushi Terada and Kazuo Kobayashi and Takeshi Nakayama and Hideaki Arima and Tsutomu Yoshihara",

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AU - Yoshihara, Tsutomu

PY - 1988

Y1 - 1988

N2 - A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.

AB - A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.

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A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM

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