Abstract
16-Mbit low-power SRAM (SuperSRAM) was developed using a new memory cell technology which makes use of DRAM technology and TFT technology, which has a record of actual performance in SRAM. For SRAM, the problems of soft errors and operation at the lower limits of Vcc have manifested at the increasing levels of miniaturization, and increases in capacity have become increasingly difficult. Nonetheless, complete compatibility with asynchronous SRAM has been implemented with the free use of circuit technology, while various problems have been resolved without cost increases using DRAM memory cell technology, which reduces surface area. The characteristics of such devices are discussed predominantly from the perspective of design.
Original language | English |
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Pages (from-to) | 32-41 |
Number of pages | 10 |
Journal | Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi) |
Volume | 90 |
Issue number | 9 |
DOIs | |
Publication status | Published - 2007 Sept |
Keywords
- Low-voltage operation
- Small-area SRAM memory cells
- Soft error-free
- SRAM
- SuperSRAM
ASJC Scopus subject areas
- Electrical and Electronic Engineering