A novel model for computing the effective capacitance of CMOS gates with interconnect loads

Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue; Junfa Mao

doi:10.1093/ietfec/e88-a.10.2562

A novel model for computing the effective capacitance of CMOS gates with interconnect loads

Zhangcai Huang^*, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C_eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C_eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C_eff. The introduction of Integration Approximation results in C_eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

Original language	English
Pages (from-to)	2562-2568
Number of pages	7
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E88-A
Issue number	10
DOIs	https://doi.org/10.1093/ietfec/e88-a.10.2562
Publication status	Published - 2005 Oct

Keywords

CMOS inverter
Effective capacitance
Interconnect loads
Static timing analysis, gate delay

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Information Systems

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10.1093/ietfec/e88-a.10.2562

Cite this

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abstract = "In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.",

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AU - Huang, Zhangcai

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

AU - Mao, Junfa

PY - 2005/10

Y1 - 2005/10

N2 - In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

AB - In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

KW - CMOS inverter

KW - Effective capacitance

KW - Interconnect loads

KW - Static timing analysis, gate delay

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A novel model for computing the effective capacitance of CMOS gates with interconnect loads

Abstract

Keywords

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