A novel SRAM structure for leakage power suppression in 45nm technology

Sui Huang; Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/ICCCAS.2008.4657953

A novel SRAM structure for leakage power suppression in 45nm technology

Sui Huang^*, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully conside. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] (2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

Original language	English
Title of host publication	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages	1070-1074
Number of pages	5
DOIs	https://doi.org/10.1109/ICCCAS.2008.4657953
Publication status	Published - 2008
Event	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province Duration: 2008 May 25 → 2008 May 27

Other

Other	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
City	Xiamen, Fujian Province
Period	08/5/25 → 08/5/27

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ICCCAS.2008.4657953

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Huang, S, Huang, Z, Kurokawa, A & Inoue, Y 2008, A novel SRAM structure for leakage power suppression in 45nm technology. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657953, pp. 1070-1074, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657953

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title = "A novel SRAM structure for leakage power suppression in 45nm technology",

abstract = "Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully conside. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] (2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.",

author = "Sui Huang and Zhangcai Huang and Atsushi Kurokawa and Yasuaki Inoue",

year = "2008",

doi = "10.1109/ICCCAS.2008.4657953",

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isbn = "9781424420636",

pages = "1070--1074",

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note = "2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 ; Conference date: 25-05-2008 Through 27-05-2008",

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AU - Huang, Sui

AU - Huang, Zhangcai

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

PY - 2008

Y1 - 2008

N2 - Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully conside. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] (2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

AB - Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully conside. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] (2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

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A novel SRAM structure for leakage power suppression in 45nm technology

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