A novel structure of energy efficiency charge recovery logic

Yimeng Zhang; Leona Okamura; Mengshu Huang; Tsutomu Yoshihara

doi:10.1109/ICGCS.2010.5543082

A novel structure of energy efficiency charge recovery logic

Yimeng Zhang^*, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

Original language	English
Title of host publication	1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages	133-136
Number of pages	4
DOIs	https://doi.org/10.1109/ICGCS.2010.5543082
Publication status	Published - 2010
Event	1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai Duration: 2010 Jun 21 → 2010 Jun 23

Other

Other	1st International Conference on Green Circuits and Systems, ICGCS 2010
City	Shanghai
Period	10/6/21 → 10/6/23

Keywords

AC power supply
Charge-recovery logic
Low energy dissipation

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICGCS.2010.5543082

Cite this

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title = "A novel structure of energy efficiency charge recovery logic",

abstract = "A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.",

keywords = "AC power supply, Charge-recovery logic, Low energy dissipation",

author = "Yimeng Zhang and Leona Okamura and Mengshu Huang and Tsutomu Yoshihara",

year = "2010",

doi = "10.1109/ICGCS.2010.5543082",

language = "English",

isbn = "9781424468775",

pages = "133--136",

booktitle = "1st International Conference on Green Circuits and Systems, ICGCS 2010",

note = "1st International Conference on Green Circuits and Systems, ICGCS 2010 ; Conference date: 21-06-2010 Through 23-06-2010",

}

TY - GEN

T1 - A novel structure of energy efficiency charge recovery logic

AU - Zhang, Yimeng

AU - Okamura, Leona

AU - Huang, Mengshu

AU - Yoshihara, Tsutomu

PY - 2010

Y1 - 2010

N2 - A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

AB - A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

KW - AC power supply

KW - Charge-recovery logic

KW - Low energy dissipation

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DO - 10.1109/ICGCS.2010.5543082

M3 - Conference contribution

AN - SCOPUS:77956579735

SN - 9781424468775

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EP - 136

BT - 1st International Conference on Green Circuits and Systems, ICGCS 2010

T2 - 1st International Conference on Green Circuits and Systems, ICGCS 2010

Y2 - 21 June 2010 through 23 June 2010

ER -

A novel structure of energy efficiency charge recovery logic

Abstract

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Keywords

ASJC Scopus subject areas

UN SDGs

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