A parallelizing compiler cooperative heterogeneous multicore processor architecture

Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara

doi:10.1007/978-3-642-24568-8_11

A parallelizing compiler cooperative heterogeneous multicore processor architecture

Yasutaka Wada^*, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Heterogeneous multicore architectures, integrating several kinds of accelerator cores in addition to general purpose processor cores, have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high application software productivity, and low power consumption on heterogeneous multicores, cooperation between an architecture and a parallelizing compiler is important. This paper proposes a compiler cooperative heterogeneous multicore architecture and parallelizing compilation scheme for it. Performance of the proposed scheme is evaluated on the heterogeneous multicore integrating Hitachi and Renesas' SH4A processor cores and Hitachi's FE-GA accelerator cores, using an MP3 encoder. The heterogeneous multicore gives us 14.34 times speedup with two SH4As and two FE-GAs, and 26.05 times speedup with four SH4As and four FE-GAs against sequential execution with a single SH4A. The cooperation between the heterogeneous multicore architecture and the parallelizing compiler enables to achieve high performance in a short development period.

Original language	English
Title of host publication	Transactions on High-Performance Embedded Architectures and Compilers IV
Publisher	Springer Verlag
Pages	215-233
Number of pages	19
ISBN (Print)	9783642245671
DOIs	https://doi.org/10.1007/978-3-642-24568-8_11
Publication status	Published - 2011

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	6760 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-642-24568-8_11

Cite this

Wada, Y., Hayashi, A., Masuura, T., Shirako, J., Nakano, H., Shikano, H., Kimura, K., & Kasahara, H. (2011). A parallelizing compiler cooperative heterogeneous multicore processor architecture. In Transactions on High-Performance Embedded Architectures and Compilers IV (pp. 215-233). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6760 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-642-24568-8_11

A parallelizing compiler cooperative heterogeneous multicore processor architecture. / Wada, Yasutaka; Hayashi, Akihiro; Masuura, Takeshi et al.
Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Verlag, 2011. p. 215-233 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6760 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wada, Y, Hayashi, A, Masuura, T, Shirako, J, Nakano, H, Shikano, H, Kimura, K & Kasahara, H 2011, A parallelizing compiler cooperative heterogeneous multicore processor architecture. in Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 6760 LNCS, Springer Verlag, pp. 215-233. https://doi.org/10.1007/978-3-642-24568-8_11

Wada Y, Hayashi A, Masuura T, Shirako J, Nakano H, Shikano H et al. A parallelizing compiler cooperative heterogeneous multicore processor architecture. In Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Verlag. 2011. p. 215-233. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-24568-8_11

Wada, Yasutaka ; Hayashi, Akihiro ; Masuura, Takeshi et al. / A parallelizing compiler cooperative heterogeneous multicore processor architecture. Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Verlag, 2011. pp. 215-233 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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AB - Heterogeneous multicore architectures, integrating several kinds of accelerator cores in addition to general purpose processor cores, have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high application software productivity, and low power consumption on heterogeneous multicores, cooperation between an architecture and a parallelizing compiler is important. This paper proposes a compiler cooperative heterogeneous multicore architecture and parallelizing compilation scheme for it. Performance of the proposed scheme is evaluated on the heterogeneous multicore integrating Hitachi and Renesas' SH4A processor cores and Hitachi's FE-GA accelerator cores, using an MP3 encoder. The heterogeneous multicore gives us 14.34 times speedup with two SH4As and two FE-GAs, and 26.05 times speedup with four SH4As and four FE-GAs against sequential execution with a single SH4A. The cooperation between the heterogeneous multicore architecture and the parallelizing compiler enables to achieve high performance in a short development period.

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A parallelizing compiler cooperative heterogeneous multicore processor architecture

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