A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kazushi Kawamura; Sho Tanaka; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ISCAS.2013.6572200

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

Original language	English
Title of host publication	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages	1736-1739
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572200
Publication status	Published - 2013
Event	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China Duration: 2013 May 19 → 2013 May 23

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/Territory	China
City	Beijing
Period	13/5/19 → 13/5/23

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2013.6572200

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A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. / Kawamura, Kazushi; Tanaka, Sho; Yanagisawa, Masao et al.
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 1736-1739 6572200 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kawamura, K, Tanaka, S, Yanagisawa, M & Togawa, N 2013, A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. in 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013., 6572200, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1736-1739, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 13/5/19. https://doi.org/10.1109/ISCAS.2013.6572200

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AB - In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

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A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

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