A performance enhanced dual-switch Network-on-Chip architecture

Lian Zeng; Takahiro Watanabe

doi:10.1109/ASPDAC.2015.7058983

A performance enhanced dual-switch Network-on-Chip architecture

Lian Zeng, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-74
Number of pages	6
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058983
Publication status	Published - 2015 Mar 11
Externally published	Yes
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 2015 Jan 19 → 2015 Jan 22

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	15/1/19 → 15/1/22

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

Access to Document

10.1109/ASPDAC.2015.7058983

Cite this

Zeng, L., & Watanabe, T. (2015). A performance enhanced dual-switch Network-on-Chip architecture. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 69-74). Article 7058983 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058983

A performance enhanced dual-switch Network-on-Chip architecture. / Zeng, Lian; Watanabe, Takahiro.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 69-74 7058983 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zeng, L & Watanabe, T 2015, A performance enhanced dual-switch Network-on-Chip architecture. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058983, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 69-74, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7058983

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AB - Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

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A performance enhanced dual-switch Network-on-Chip architecture

Abstract

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ASJC Scopus subject areas

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