A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

Saki Tajima; Masao Yanagisawa; Youhua Shi

doi:10.1109/PrimeAsia47521.2019.8950738

A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

Saki Tajima, Masao Yanagisawa, Youhua Shi

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.

Original language	English
Title of host publication	Proceedings - PrimeAsia 2019
Subtitle of host publication	2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption
Publisher	IEEE Computer Society
Pages	53-56
Number of pages	4
ISBN (Electronic)	9781728130552
DOIs	https://doi.org/10.1109/PrimeAsia47521.2019.8950738
Publication status	Published - 2019 Nov
Event	2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019 - Bangkok, Thailand Duration: 2019 Nov 11 → 2019 Nov 14

Publication series

Name	Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Volume	2019-November
ISSN (Print)	2159-2144
ISSN (Electronic)	2159-2160

Conference

Conference	2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019
Country/Territory	Thailand
City	Bangkok
Period	19/11/11 → 19/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Education

Access to Document

10.1109/PrimeAsia47521.2019.8950738

Cite this

Tajima, S., Yanagisawa, M., & Shi, Y. (2019). A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability. In Proceedings - PrimeAsia 2019: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption (pp. 53-56). Article 8950738 (Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics; Vol. 2019-November). IEEE Computer Society. https://doi.org/10.1109/PrimeAsia47521.2019.8950738

A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability. / Tajima, Saki; Yanagisawa, Masao ; Shi, Youhua.
Proceedings - PrimeAsia 2019: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption. IEEE Computer Society, 2019. p. 53-56 8950738 (Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics; Vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tajima, S, Yanagisawa, M & Shi, Y 2019, A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability. in Proceedings - PrimeAsia 2019: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption., 8950738, Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, vol. 2019-November, IEEE Computer Society, pp. 53-56, 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019, Bangkok, Thailand, 19/11/11. https://doi.org/10.1109/PrimeAsia47521.2019.8950738

Tajima S, Yanagisawa M , Shi Y. A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability. In Proceedings - PrimeAsia 2019: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption. IEEE Computer Society. 2019. p. 53-56. 8950738. (Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics). doi: 10.1109/PrimeAsia47521.2019.8950738

Tajima, Saki ; Yanagisawa, Masao ; Shi, Youhua. / A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability. Proceedings - PrimeAsia 2019: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption. IEEE Computer Society, 2019. pp. 53-56 (Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics).

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abstract = "A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.",

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AB - A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.

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A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

Abstract

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