A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

H. Koike; T. Ohsawa; S. Ikeda; T. Hanyu; H. Ohno; T. Endoh; N. Sakimura; R. Nebashi; Y. Tsuji; A. Morioka; S. Miura; H. Honjo; T. Sugibayashi

doi:10.1109/ASSCC.2013.6691046

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages	317-320
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2013.6691046
Publication status	Published - 2013 Dec 1
Externally published	Yes
Event	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore Duration: 2013 Nov 11 → 2013 Nov 13

Publication series

Name	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Country/Territory	Singapore
City	Singapore
Period	13/11/11 → 13/11/13

Keywords

Flip-flop
MPU
MTJ
Nonvolatile
Power gating

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/ASSCC.2013.6691046

Cite this

Koike, H., Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H., Endoh, T., Sakimura, N., Nebashi, R., Tsuji, Y., Morioka, A., Miura, S., Honjo, H., & Sugibayashi, T. (2013). A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop. In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 (pp. 317-320). [6691046] (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013). https://doi.org/10.1109/ASSCC.2013.6691046

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop. / Koike, H.; Ohsawa, T.; Ikeda, S. et al.
Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013. 2013. p. 317-320 6691046 (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Koike, H, Ohsawa, T, Ikeda, S, Hanyu, T, Ohno, H, Endoh, T, Sakimura, N, Nebashi, R, Tsuji, Y, Morioka, A, Miura, S, Honjo, H & Sugibayashi, T 2013, A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop. in Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013., 6691046, Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, pp. 317-320, 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, Singapore, 13/11/11. https://doi.org/10.1109/ASSCC.2013.6691046

Koike H, Ohsawa T, Ikeda S, Hanyu T, Ohno H, Endoh T et al. A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop. In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013. 2013. p. 317-320. 6691046. (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013). doi: 10.1109/ASSCC.2013.6691046

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abstract = "We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.",

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AU - Ohno, H.

AU - Endoh, T.

AU - Sakimura, N.

AU - Nebashi, R.

AU - Tsuji, Y.

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AB - We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.

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A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

Abstract

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Conference

Keywords

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