A processor core synthesis system in IP-based SoC design

Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1145/1120725.1120851

A processor core synthesis system in IP-based SoC design

Naoki Tomono^*, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

Original language	English
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	286-291
Number of pages	6
ISBN (Print)	0780387368, 9780780387362
DOIs	https://doi.org/10.1145/1120725.1120851
Publication status	Published - 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: 2005 Jan 18 → 2005 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1145/1120725.1120851

Cite this

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2005). A processor core synthesis system in IP-based SoC design. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 286-291). [1466175] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1120851

A processor core synthesis system in IP-based SoC design. / Tomono, Naoki; Kohara, Shunitsu; Uchida, Jumpei et al.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 286-291 1466175 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tomono, N, Kohara, S, Uchida, J, Miyaoka, Y, Togawa, N , Yanagisawa, M & Ohtsuki, T 2005, A processor core synthesis system in IP-based SoC design. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466175, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 286-291, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18. https://doi.org/10.1145/1120725.1120851

Tomono N, Kohara S, Uchida J, Miyaoka Y, Togawa N , Yanagisawa M et al. A processor core synthesis system in IP-based SoC design. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc. 2005. p. 286-291. 1466175. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1120725.1120851

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abstract = "This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.",

author = "Naoki Tomono and Shunitsu Kohara and Jumpei Uchida and Yuichiro Miyaoka and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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AU - Yanagisawa, Masao

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AB - This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

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A processor core synthesis system in IP-based SoC design

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