A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya; Kazuyasu Fujishima; Hideshi Miyatake; Nishimura Yasumasa; Kazunori Saito; Takayuki Matsukawa; Tsutomu Yoshihara; Takao Nakano

doi:10.1109/JSSC.1985.1052414

A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Nishimura Yasumasa, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original language	English
Pages (from-to)	909-913
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	20
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1985.1052414
Publication status	Published - 1985
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.1985.1052414

Cite this

@article{6334147937164282ba48e38d6227e032,

title = "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode",

abstract = "This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.",

author = "Masaki Kumanoya and Kazuyasu Fujishima and Hideshi Miyatake and Nishimura Yasumasa and Kazunori Saito and Takayuki Matsukawa and Tsutomu Yoshihara and Takao Nakano",

year = "1985",

doi = "10.1109/JSSC.1985.1052414",

language = "English",

volume = "20",

pages = "909--913",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

AU - Kumanoya, Masaki

AU - Fujishima, Kazuyasu

AU - Miyatake, Hideshi

AU - Yasumasa, Nishimura

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1985

Y1 - 1985

N2 - This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

AB - This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

UR - http://www.scopus.com/inward/record.url?scp=84939067947&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84939067947&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1985.1052414

DO - 10.1109/JSSC.1985.1052414

M3 - Article

AN - SCOPUS:84939067947

SN - 0018-9200

VL - 20

SP - 909

EP - 913

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this