This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.
|Number of pages||5|
|Journal||IEEE Journal of Solid-State Circuits|
|Publication status||Published - 1985|
ASJC Scopus subject areas
- Electrical and Electronic Engineering