A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Nishimura Yasumasa, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Contribution to journalArticlepeer-review


This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original languageEnglish
Pages (from-to)909-913
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 1985
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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