A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA

Tingyu Zhou, Tieyuan Pan, Zhiguo Bao, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Field-programmable gate array (FPGA) has enormous potential in the field of Integrated Circuit (IC) due to its programmability, short design cycle, and high flexibility in parallel computing. Nevertheless, increasing chip integration and shrinking transistor size lead to non-negligible power dissipation in FPGA. Specifically, leakage power dissipation issue as a crucial part of power consumption in FPGA requires being concerned urgently. In this paper, a time-based leakage-power aware algorithm (TBLA) is proposed to address the aforementioned issue on 2D dynamic partial reconfigurable FPGA. Experimental results show that the proposed TBLA algorithm reduces the leakage-power and scheduling overhead without increasing the overall execution time of an application compared to traditional algorithms.

Original languageEnglish
Title of host publication2018 5th International Conference on Systems and Informatics, ICSAI 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages501-506
Number of pages6
ISBN (Electronic)9781728101200
DOIs
Publication statusPublished - 2019 Jan 2
Event5th International Conference on Systems and Informatics, ICSAI 2018 - Nanjing, China
Duration: 2018 Nov 102018 Nov 12

Publication series

Name2018 5th International Conference on Systems and Informatics, ICSAI 2018

Conference

Conference5th International Conference on Systems and Informatics, ICSAI 2018
Country/TerritoryChina
CityNanjing
Period18/11/1018/11/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications
  • Energy Engineering and Power Technology
  • Control and Systems Engineering

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